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Disambiguation of "Ravishankar, Chirag"

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Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.

, , , , and . FPGA, page 231. ACM, (2023)

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Chirag Ashokkumar Jhala

Ravishankar Bhaskarrao Borgaonkar

 

Other publications of authors with the same name

FPGA power reduction by guarded evaluation., and . FPGA, page 157-166. ACM, (2010)EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip., , , and . FPL, page 41-48. IEEE, (2012)Raising FPGA Logic Density Through Synthesis-Inspired Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (3): 537-550 (2012)Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs., , , , , , and . FCCM, page 133-143. IEEE, (2023)Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture., , , and . FPGA, page 84-93. ACM, (2019)Parallel FPGA technology mapping using multi-core architectures., and . CCECE, page 274-279. IEEE, (2011)EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only)., , , and . FPGA, page 266. ACM, (2012)Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms., , , and . ISQED, page 617-624. IEEE, (2012)FPGA power reduction by guarded evaluation considering physical information., , and . VLSI-SoC, page 271-274. IEEE, (2012)IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck., , , , and . ICCAD, page 1-9. IEEE, (2023)