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A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC., , , , и . J. Signal Process. Syst., 82 (1): 69-89 (2016)Adaptive postprocessors with DCT-based block classifications., , и . IEEE Trans. Circuits Syst. Video Technol., 13 (5): 365-375 (2003)DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation., , , и . IEEE Trans. Circuits Syst. Video Technol., 15 (5): 694-703 (2005)Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator., , и . AICAS, стр. 238-241. IEEE, (2022)Reconfigurable Deep Learning Accelerator Hardware Architecture Design for Sparse CNN., , и . ICCE-TW, стр. 1-2. IEEE, (2021)Quantized Lite Convolutional Neural Network Hardware Accelerator Design with FPGA for Face Direction Recognition., , , , и . ICCE-TW, стр. 61-62. IEEE, (2022)Cordic Based Hardware Implementation for Object Region Layer of Yolo V2., и . ICCE-TW, стр. 1-2. IEEE, (2020)System Integration and Optimization of AI Hardware Acceleration Architecture for Object Detection., , и . ICCE-Taiwan, стр. 93-94. IEEE, (2023)A real-time architecture of multiple features extraction for vehicle verification., , и . APCCAS, стр. 615-618. IEEE, (2014)An efficient background extraction and object segmentation algorithm for realtime applications., , и . APCCAS, стр. 659-662. IEEE, (2012)