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Design, Debug, Deploy: The Creation of Configurable Computing Applications., , and . J. Signal Process. Syst., 53 (1-2): 187-196 (2008)Evaluating Performance of Prefetching Second Level Caches., , and . SIGMETRICS Perform. Evaluation Rev., 20 (4): 31-42 (1993)Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAs., , , and . FPGA, page 306-307. ACM, (2019)Tincr - A custom CAD tool framework for Vivado., and . ReConFig, page 1-6. IEEE, (2014)FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda.. ARC, volume 5453 of Lecture Notes in Computer Science, page 1. Springer, (2009)JHDLBits: The Merging of Two Worlds., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 414-423. Springer, (2004)A Parallel FFT Architecture for FPGAs., and . FPL, volume 3203 of Lecture Notes in Computer Science, page 948-953. Springer, (2004)Vivado design interface: An export/import capability for Vivado FPGA designs., and . FPL, page 1-7. IEEE, (2017)A Hardware-Friendly Adaptive Tensor Based Optical Flow Algorithm., , and . ISVC (2), volume 4842 of Lecture Notes in Computer Science, page 43-51. Springer, (2007)The structure and operation of a relational database system in a cell-oriented integrated circuit design system., , , and . DAC, page 117-125. ACM/IEEE, (1984)