( en | de | ru )

 

Disambiguation of "Boncalo, Oana"

Author of the publication

copydeleteadd this publication to your clipboard
Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.

, , , , and . DSD, page 132-137. IEEE Computer Society, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Oana Schüszler

Oana Stan

Oana Lorintiu

Oana Goga

Oana Coban

 

Other publications of authors with the same name

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment., , , , and . DSD, page 634-640. IEEE Computer Society, (2007)An FPGA sliding window-based architecture harris corner detector., , and . FPL, page 1-4. IEEE, (2014)Quantum circuit's reliability assessment with VHDL-based simulated fault injection., , , and . Microelectron. Reliab., 50 (2): 304-311 (2010)Layered LDPC decoder in-order message access scheduling: a case study., and . SACI, page 193-198. IEEE, (2020)Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques., , and . DDECS, page 149-152. IEEE Computer Society, (2015)Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding., , and . DSD, page 104-109. IEEE Computer Society, (2018)Reliability analysis of memory centric LDPC decoders under probabilistic storage failures., , , and . ICECS, page 592-595. IEEE, (2016)Simulated Fault Injection for Quantum Circuits Based on Simulator Commands., , , , and . SACI, page 245-250. IEEE, (2007)Cost effective FPGA probabilistic fault emulation., , , and . NORCHIP, page 1-4. IEEE, (2014)SRT radix-2 dividers with (5, 4) redundant representation of partial remainder., and . NORCHIP, page 1-5. IEEE, (2013)