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Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators.

, , , and . PRIME, page 373-376. IEEE, (2022)

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Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators., , , and . PRIME, page 373-376. IEEE, (2022)A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms., , , , , and . IEEE Access, (2021)VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (2): 177-186 (2022)Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative., , , , , and . ApplePies, volume 1110 of Lecture Notes in Electrical Engineering, page 378-385. Springer, (2023)A PUF-Based Secure Boot for RISC-V Architectures., , , , , , and . ApplePies, volume 1110 of Lecture Notes in Electrical Engineering, page 87-94. Springer, (2023)Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip., , , , and . PRIME, page 181-184. IEEE, (2023)Enhanced Soft GPU Architecture for FPGAs., , , , and . PRIME, page 177-180. IEEE, (2023)A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture., , and . DTIS, page 1-6. IEEE, (2021)