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Modulo scheduling with integrated register spilling for clustered VLIW architectures.

, , , and . MICRO, page 160-169. ACM/IEEE Computer Society, (2001)

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A fast and accurate framework to analyze and optimize cache memory behavior., , , and . ACM Trans. Program. Lang. Syst., 26 (2): 263-300 (2004)Using Sacks to Organize Registers in VLIW Machines., , , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 628-639. Springer, (1994)Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes., , , , and . ISHPC, volume 2858 of Lecture Notes in Computer Science, page 113-126. Springer, (2003)Allocating Lifetimes to Queues in Software Pipelined Architectures., , and . Euro-Par, volume 1300 of Lecture Notes in Computer Science, page 1066-1073. Springer, (1997)Hybrid multithreading for VLIW processors., , and . CASES, page 37-46. ACM, (2009)Merge Logic for Clustered Multithreaded VLIW Processors., , and . DSD, page 353-360. IEEE Computer Society, (2007)Heuristics for Register-Constrained Software Pipelining., , and . MICRO, page 250-261. ACM/IEEE Computer Society, (1996)Hypernode reduction modulo scheduling., , , and . MICRO, page 350-360. ACM / IEEE Computer Society, (1995)Distributed Modulo Scheduling., , and . HPCA, page 130-134. IEEE Computer Society, (1999)Partitioned Schedules for Clustered VLIW Architectures., , and . IPPS/SPDP, page 386-391. IEEE Computer Society, (1998)