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Disambiguation of "Galton, Ian"

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A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2013-2023 (2015)

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Max Iann

Nadia Ianeva

Gheorghe Iancu

Enrico Iannone

Alen Ianni

 

Other publications of authors with the same name

One-bit Dithering in Delta-Sigma Modulator-based D/A Conversion.. ISCAS, page 1310-1313. IEEE, (1993)Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (3): 492-503 (2007)A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal., , , and . IEEE J. Solid State Circuits, 33 (12): 2042-2053 (1998)A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation., , and . IEEE J. Solid State Circuits, 39 (1): 49-62 (2004)Addition to Ä Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation"., , and . IEEE J. Solid State Circuits, 40 (2): 559 (2005)An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC., , and . IEEE J. Solid State Circuits, 36 (3): 339-348 (2001)Digital Background Correction of Harmonic Distortion in Pipelined ADCs., and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (9): 1885-1895 (2006)Why Dynamic-Element-Matching DACs Work.. IEEE Trans. Circuits Syst. II Express Briefs, 57-II (2): 69-74 (2010)Simplified Logic for Tree-Structure Segmented DEM Encoders., , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1029-1033 (2016)A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error., , and . IEEE J. Solid State Circuits, 54 (8): 2219-2229 (2019)