From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark., , , , и . Frontiers Artif. Intell., (2021)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2306-2319 (2021)A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling., , , и . ESSCIRC, стр. 101-104. IEEE, (2022)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training., , , , и . CoRR, (2020)Architecture and Circuit Design Optimization for Compute-In-Memory.. Georgia Institute of Technology, Atlanta, GA, USA, (2023)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/70137).XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption., , , , и . ICCAD, стр. 77:1-77:6. IEEE, (2020)A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays., , , и . VLSI Technology and Circuits, стр. 266-267. IEEE, (2022)Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories., , , , и . DATE, стр. 1025-1030. IEEE, (2020)CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training., , , и . MEMSYS, стр. 490-496. ACM, (2019)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips., , , , , , , , , и 13 other автор(ы). ISSCC, стр. 240-242. IEEE, (2020)