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GPU-based timing-aware test generation for small delay defects., , , , , и . ETS, стр. 1-2. IEEE, (2014)A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms., , и . DATE, стр. 1427-1430. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A new hybrid solution to boost SAT solver performance., и . DATE, стр. 1307-1313. EDA Consortium, San Jose, CA, USA, (2007)RTL functional test generation using factored concolic execution., и . ITC, стр. 1-10. IEEE, (2017)Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors., , , и . J. Electron. Test., 19 (4): 437-445 (2003)Error Diagnosis of Sequential Circuits Using Region-Based Model., и . J. Electron. Test., 21 (2): 115-126 (2005)On Non-Statistical Techniques for Fast Fault Coverage Estimation.. J. Electron. Test., 15 (3): 239-254 (1999)Peak power estimation of VLSI circuits: new peak power measures., , и . IEEE Trans. Very Large Scale Integr. Syst., 8 (4): 435-439 (2000)A SMT-based diagnostic test generation method for combinational circuits., , , и . VTS, стр. 215-220. IEEE Computer Society, (2012)Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract., , и . ACM Great Lakes Symposium on VLSI, стр. 331-332. ACM, (2013)