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Disambiguation of "U, Seng-Pan"

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A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (8): 1966-1976 (2017)

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Peter Seng

Stefan Seng

Katja Seng

Gerhard Seng

Helmut Seng

 

Other publications of authors with the same name

Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (9): 903-907 (2016)Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (2): 489-501 (2019)Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (6): 1819-1829 (2018)A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration., , , , and . IEEE J. Solid State Circuits, 53 (3): 850-860 (2018)60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration., , , , , , , and . IEEE J. Solid State Circuits, 52 (10): 2576-2588 (2017)20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control., , , and . ISSCC, page 342-343. IEEE, (2017)A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS., , , , and . A-SSCC, page 285-288. IEEE, (2017)A digital LDO with transient enhancement and limit cycle oscillation reduction., , , and . APCCAS, page 25-28. IEEE, (2016)A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC., , , , and . IEEE J. Solid State Circuits, 51 (2): 365-377 (2016)A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS., , and . IEEE J. Solid State Circuits, 39 (1): 87-99 (2004)