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An Energy-Efficient Processor Architecture for Embedded Systems., , , , and . IEEE Comput. Archit. Lett., 7 (1): 29-32 (2008)Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors., , , and . HPCA, page 424-434. IEEE, (2020)StatTask: reuse distance analysis for task-based applications., , and . RAPIDO@HiPEAC, page 1:1-1:7. ACM, (2015)Every walk's a hit: making page walks single-access cache hits., , , and . ASPLOS, page 128-141. ACM, (2022)TaskInsight: Understanding Task Schedules Effects on Memory and Performance., , , and . PMAM@PPoPP, page 11-20. ACM, (2017)Register pointer architecture for efficient embedded processors., , , , , and . DATE, page 600-605. EDA Consortium, San Jose, CA, USA, (2007)Modeling and optimizing NUMA effects and prefetching with machine learning., , , , , and . ICS, page 34:1-34:13. ACM, (2020)A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006., , and . ACM Trans. Archit. Code Optim., 18 (2): 24:1-24:20 (2021)FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors., , , and . DATE, page 716-721. IEEE, (2019)Hierarchical Instruction Register Organization., , , , and . IEEE Comput. Archit. Lett., 7 (2): 41-44 (2008)