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An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization.

, , , and . IPDPS, page 83-94. IEEE Computer Society, (2012)

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FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2032-2045 (2016)Efficient GPU Spatial-Temporal Multitasking., , , , and . IEEE Trans. Parallel Distributed Syst., 26 (3): 748-760 (2015)Integrated CUDA-to-FPGA Synthesis with Network-on-Chip., , , , , and . FCCM, page 21-24. IEEE Computer Society, (2014)AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS., , , and . FCCM, page 127-130. IEEE Computer Society, (2016)Dynamic Binding and Scheduling of Firm-Deadline Tasks on Heterogeneous Compute Resources., , , and . RTCSA, page 275-280. IEEE Computer Society, (2010)Register and thread structure optimization for GPUs., , , and . ASP-DAC, page 461-466. IEEE, (2013)Performance metrics for hybrid multi-tasking systems., , , and . FPL, page 547-550. IEEE, (2009)Fast and effective placement and routing directed high-level synthesis for FPGAs., , , and . FPGA, page 1-10. ACM, (2014)SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection., , , , , , , , , and 2 other author(s). CoRR, (2019)High-level synthesis of multiple dependent CUDA kernels on FPGA., , , , and . ASP-DAC, page 305-312. IEEE, (2013)