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Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection.

, , , , , and . ICECS, page 74-77. IEEE, (2007)

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Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 461-472. Kluwer, (2001)On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 425-436. Kluwer, (2001)On-chip analog output response compaction., , and . ED&TC, page 568-572. IEEE Computer Society, (1997)Automatic building of structured geological models., , , , , , and . Symposium on Solid Modeling and Applications, page 59-69. ACM, (2004)N-Dimensional Gregory-Bezier for N-Dimensional Cellular Complexes., , and . WSCG (Short Papers), page 16-23. (2001)Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors., , , , and . J. Electron. Test., 20 (3): 257-267 (2004)On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area., , , , and . LATW, page 112-117. IEEE, (2001)A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs., , , and . Asian Test Symposium, page 383-387. IEEE Computer Society, (1998)A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs., , and . VLSI Design, page 352-353. IEEE Computer Society, (1992)Bridging fault coverage improvement by power supply control., , and . VTS, page 338-343. IEEE Computer Society, (1996)