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Disambiguation of "Ikeda, Namiko"

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FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing.

, , , , , and . ASAP, page 29-32. IEEE, (2020)

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Yukihiro Ikeda

Mitsuyoshi Ikeda

Shingo Ikeda

Yoshikazu Ikeda

Wakako Ikeda-Ohtsubo

 

Other publications of authors with the same name

Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction., , , , , and . GLOBECOM, page 1-5. IEEE, (2011)Fingerprint Image Enhancement by Pixel-Parallel Processing., , , , , , , and . ICPR (3), page 752-755. IEEE Computer Society, (2002)Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI., , , , , , , and . IEICE Trans. Electron., 90-C (10): 1892-1899 (2007)Traffic Monitoring System for 100-Gbps Virtualized Optical Networks., , , , , , and . OFC, page 1-3. IEEE, (2022)High-speed sorted-table search scheme for network processing., , , and . APCC, page 616-620. IEEE, (2015)Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier., , , , , , , , , and . IEICE Trans. Electron., 89-C (4): 540-550 (2006)A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification., , , , , , , , and . CICC, page 261-264. IEEE, (2002)FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing., , , , , and . ASAP, page 29-32. IEEE, (2020)Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs., , , , , and . FPL, page 639-642. IEEE, (2012)FPGA-based network microburst analysis system with efficient packet capturing., , , , , and . JOCN, 13 (10): E72-E80 (2021)