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RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU.

, , , and . CoRR, (2021)

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Exposing Abstraction-Level Interactions with a Parallel Ray Tracer., , , , , , , , , and 7 other author(s). WCAE@ISCA, page 5:1-5:8. ACM, (2019)peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter., , , , and . DCIS, page 1-6. IEEE, (2022)Fast-track cache: a huge racetrack memory L1 data cache., , , , and . ICS, page 23:1-23:12. ACM, (2022)Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance., , , and . IEEE Trans. Computers, 68 (10): 1442-1454 (2019)RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU., , , and . CoRR, (2021)An Aging-Aware GPU Register File Design Based on Data Redundancy., , , , and . IEEE Trans. Computers, 68 (1): 4-20 (2019)DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files., , and . IEEE Access, (2020)A learning experience toward the understanding of abstraction-level interactions in parallel applications., , , , , , , , and . J. Parallel Distributed Comput., (2021)On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators., , , and . DSD, page 138-145. IEEE, (2023)Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators., , , and . J. Syst. Archit., (2022)