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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. Taylor, and R. Dreslinski. VLSI Circuits, page 30-. IEEE, (2019)

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A Neuro-Symbolic Approach to Multi-Agent RL for Interpretability and Probabilistic Decision Making.C. Subramanian, M. Liu, N. Khan, J. Lenchner, A. Amarnath, S. Swaminathan, R. Riegel, and A. Gray. CoRR, (2024)R2D3: A Reliability Engine for 3D Parallel Systems.J. Bagherzadeh, A. Amarnath, J. Tan, S. Pal, and R. Dreslinski. DAC, page 1-6. IEEE, (2020)Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles.A. Amarnath, S. Pal, H. Kassa, A. Vega, A. Buyuktosunoglu, H. Franke, J. Wellman, R. Jr., and P. Bose. IEEE Comput. Archit. Lett., 20 (2): 82-85 (2021)A Holistic Solution for Reliability of 3D Parallel Systems.J. Bagherzadeh, A. Amarnath, J. Tan, S. Pal, and R. Dreslinski. ACM J. Emerg. Technol. Comput. Syst., 18 (1): 23:1-23:27 (2022)A carbon nanotube transistor based RISC-V processor using pass transistor logic.A. Amarnath, S. Feng, S. Pal, T. Ajayi, A. Rovinski, and R. Dreslinski. ISLPED, page 1-6. IEEE, (2017)A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors.H. Kim, A. Amarnath, J. Bagherzadeh, N. Talati, and R. Dreslinski. ACM J. Emerg. Technol. Comput. Syst., 17 (3): 27:1-27:44 (2021)A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.S. Pal, D. Park, S. Feng, P. Gao, J. Tan, A. Rovinski, S. Xie, C. Zhao, A. Amarnath, T. Wesley and 8 other author(s). VLSI Circuits, page 150-. IEEE, (2019)STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.A. Vega, A. Amarnath, J. Wellman, H. Kassa, S. Pal, H. Franke, A. Buyuktosunoglu, R. Dreslinski, and P. Bose. CoRR, (2020)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.S. Davidson, S. Xie, C. Torng, K. Al-Hawaj, A. Rovinski, T. Ajayi, L. Vega, C. Zhao, R. Zhao, S. Dai and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.S. Pal, A. Amarnath, S. Feng, M. O'Boyle, R. Dreslinski, and C. Dubach. MICRO, page 1005-1021. ACM, (2021)

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Disambiguation of "Amarnath, Aporva"

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

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Disambiguation of "Amarnath, Aporva"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.