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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. Taylor, and R. Dreslinski. VLSI Circuits, page 30-. IEEE, (2019)

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Dustin Stansbury

Richmond Lennox

Tania Richmond

Richmond Repgen

Gudrun Richmond

Other publications of authors with the same name

Classifying Computations on Multi-Tenant FPGAs.M. Gobulukoglu, C. Drewes, W. Hunter, R. Kastner, and D. Richmond. DAC, page 1261-1266. IEEE, (2021)Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler.D. Richmond, J. Blackstone, M. Hogains, K. Thai, and R. Kastner. FCCM, page 21-24. IEEE Computer Society, (2016)Everyone's a Critic: A Tool for Exploring RISC-V Projects.D. Richmond, M. Barrow, and R. Kastner. FPL, page 260-264. IEEE Computer Society, (2018)Classifying Computations on Multi-Tenant FPGAs.M. Gobulukoglu, C. Drewes, B. Hunter, D. Richmond, and R. Kastner. FPGA, page 227. ACM, (2021)A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri and 11 other author(s). VLSI Circuits, page 30-. IEEE, (2019)A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems.L. Cheng, P. Pan, Z. Zhao, K. Ranjan, J. Weber, B. Veluri, S. Ehsani, M. Ruttenberg, D. Jung, P. Ivanov and 4 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1620-1635 (2022)PynqCopter - An Open-source FPGA Overlay for UAVs.B. Cain, Z. Merchant, I. Avendano, D. Richmond, and R. Kastner. IEEE BigData, page 2491-2498. IEEE, (2018)Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures.A. Brahmakshatriya, E. Furst, V. Ying, C. Hsu, C. Hong, M. Ruttenberg, Y. Zhang, D. Jung, D. Richmond, M. Taylor and 4 other author(s). ISCA, page 429-442. IEEE, (2021)Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories.L. Cheng, M. Ruttenberg, D. Jung, D. Richmond, M. Taylor, M. Oskin, and C. Batten. ASPLOS (3), page 46-58. ACM, (2023)Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters.C. Drewes, O. Weng, K. Ryan, B. Hunter, C. McCarty, R. Kastner, and D. Richmond. FPGA, page 111-122. ACM, (2023)

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Disambiguation of "Richmond, Dustin"

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Please choose a person to relate this publication to

Dustin Stansbury

Richmond Lennox

Tania Richmond

Richmond Repgen

Gudrun Richmond

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Richmond, Dustin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Please choose a person to relate this publication to

Dustin Stansbury

Richmond Lennox

Tania Richmond

Richmond Repgen

Gudrun Richmond

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.