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Disambiguation of "Chouliaras, Vassilios A."

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High-performance arithmetic coding VLSI macro for the H264 video compression standard.

, and . IEEE Trans. Consumer Electronics, 51 (1): 144-151 (2005)

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Vassilios Iossifidis

Vassilios Vadokas

Vassilios Meladinis

Vassilios Iakovakis

Vassilios Papadopoulos

 

Other publications of authors with the same name

An efficient multiple precision floating-point Multiply-Add Fused unit., , and . Microelectron. J., (2016)Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards., , , and . SIP, page 39-44. IASTED/ACTA Press, (2005)A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding., and . IEEE Trans. Computers, 54 (11): 1345-1359 (2005)Dynamic Voltage Scaling in a FPGA-based System-on-Chip., , and . FPL, page 459-462. IEEE, (2007)An efficient multiple precision floating-point multiplier., , and . ICECS, page 153-156. IEEE, (2011)Investigation Of A New Genetic Algorithm Designed For System-On-Chip Realization., , and . IEEE Congress on Evolutionary Computation, page 2981-2987. IEEE, (2006)Development of Sensorised Resistance Band for Objective Exercise Measurement: Activities Classification Trial., , , , and . EMBC, page 3942-3945. IEEE, (2018)LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support., and . ISVLSI, page 122-126. IEEE Computer Society, (2010)High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures., , , , and . ICECS, page 146-149. IEEE, (2007)Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads., , , , and . Microprocess. Microsystems, 37 (8-D): 1122-1143 (2013)