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Architectural design and analysis toolbox to implement shortest path algorithms in hardware.

, , , and . ISCAS (3), page 224-227. IEEE, (2003)

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A Hardware Efficient Technique for Rapid Lumen Segmentation from Endoscopic Images., , and . JCIS, page 716-719. JCIS / Association for Intelligent Machinery, Inc., (2002)Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits., , and . ISCAS, page 2628-2631. IEEE, (2014)Low-complexity pruning for accelerating corner detection., , , and . ISCAS, page 1684-1687. IEEE, (2012)Instruction set customization for area-constrained FPGA designs., , , and . SoCC, page 329-334. IEEE, (2011)Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays., , , and . ISCAS, page 2424-2427. IEEE, (2013)Partial rerouting algorithm for reconfigurable VLSI arrays., and . ISCAS (5), page 641-644. IEEE, (2003)Adaptive Window Strategy for High-Speed and Robust KLT Feature Tracker., , , and . PSIVT, volume 9431 of Lecture Notes in Computer Science, page 355-367. Springer, (2015)Rapid estimation of DSPs utilization for efficient high-level synthesis., , and . DSP, page 1261-1265. IEEE, (2015)High-throughput image rotation using sign-prediction based redundant cordic algorithm., , and . ICIP, page 2833-2836. IEEE, (2004)Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs., , , and . ReConFig, page 1-8. IEEE, (2018)