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Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

Q. Zhao, Y. Liu, W. Sun, J. Zhao, H. Yao, X. Guo, and H. Yang. DAC, page 80:1-80:6. ACM, (2017)

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Zhao Zhao

Yanning Zhao

Hertz-level ultra-stable laser and its application to high precision spectroscopyY. Zhao. Uni Erlangen-Nürnberg, (2009)

Su Zhao

Xiaojian Zhao

Li Zhao

Other publications of authors with the same name

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.Q. Zhao, Y. Liu, W. Sun, J. Zhao, H. Yao, X. Guo, and H. Yang. DAC, page 80:1-80:6. ACM, (2017)An effective hybrid genetic algorithm with flexible allowance technique for constrained engineering design optimization.J. Zhao, L. Wang, P. Zeng, and W. hui Fan. Expert Syst. Appl., 39 (5): 6041-6051 (2012)System architecture of a train sensor network for automatic train safety monitoring.G. Cai, J. Zhao, Q. Song, and M. Zhou. Comput. Ind. Eng., (2019)Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.Q. Zhao, W. Sun, J. Zhao, J. Zhao, H. Yao, T. Ho, X. Guo, H. Yang, and Y. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (11): 2043-2057 (2019)Optimal Decision-making Method of Transportation Route Based on Information Gain.T. Shang, Z. Liang, J. Yang, and J. Zhao. IWCMC, page 523-526. IEEE, (2021)An 18-bit 1-GS/s time interleaved analog-to-digital converter with timing skew calibration based on an adaptive genetic algorithm.J. Zhao, J. Zhang, Y. Zhang, C. Liu, Z. Xi, and X. Luo. Int. J. Circuit Theory Appl., 51 (11): 5470-5483 (November 2023)A Novel Electromechanical Transient Analysis Technique of VSC-MTDC Considering DC-PCC and its Application to AC/DC Hybrid System Simulation.T. Zhou, Z. Chen, J. Zhao, C. Xu, and X. Teng. IEEE Access, (2019)Inkjet printing narrow fine Ag lines on surface modified polymeric films.W. Tang, Y. Chen, J. Zhao, S. Chen, L. Feng, and X. Guo. NEMS, page 1171-1174. IEEE, (2013)A Fault Location Method Considering Distribution Network Partition Based on Deep Learning.J. Zhao, Z. Dai, Z. Chen, H. Ding, and P. Du. IEEM, page 1557-1562. IEEE, (2019)Joint Error Estimation and Calibration Method of Memory Nonlinear Mismatch for a Four-Channel 16-Bit TIADC System.Z. Jianwei, Y. Zhou, J. Zhao, N. Guangshan, and X. Luo. Sensors, 22 (7): 2427 (2022)

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Disambiguation of "Zhao, Jiaqing"

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Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

Please choose a person to relate this publication to

Zhao Zhao

Yanning Zhao

Su Zhao

Xiaojian Zhao

Li Zhao

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhao, Jiaqing"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

Please choose a person to relate this publication to

Zhao Zhao

Yanning Zhao

Su Zhao

Xiaojian Zhao

Li Zhao

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.