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Disambiguation of "Shinohara, Hirofumi"

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A 64-bit carry look ahead adder using pass transistor BiCMOS gates.

, , , , and . IEEE J. Solid State Circuits, 31 (6): 810-818 (1996)

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Kenichi Shinohara

Hirofumi Ishihara

Hirofumi Hosokawa

Hirofumi Ueda

Hirofumi Kumazawa

 

Other publications of authors with the same name

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology., , , , , and . ISLPED, page 15-20. ACM, (2008)A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 42 (4): 820-829 (2007)A 64-bit carry look ahead adder using pass transistor BiCMOS gates., , , , and . IEEE J. Solid State Circuits, 31 (6): 810-818 (1996)12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains., , , , , and . ESSCIRC, page 191-194. IEEE, (2011)A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement., , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (3): 564-572 (March 2024)A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement., , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , and . ICCAD, page 398-405. IEEE Computer Society, (2005)A BiCMOS wired-OR logic., , , , and . IEEE J. Solid State Circuits, 30 (6): 622-628 (June 1995)Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 918-921 (2012)Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits., , , , , and . IEEE J. Solid State Circuits, 48 (8): 1986-1994 (2013)