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Disambiguation of "Ansari, Muhammad Adil"

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Highly Efficient Test Architecture for Low-Power AI Accelerators.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (8): 2728-2738 (2022)

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Muhammad Muhammad

Firouz Adili

Kamil Adilo lu

Adil Atiser

Adil Gedikli

 

Other publications of authors with the same name

Efficient diagnosis technique for aging defects on automotive semiconductor chips., , , , and . ETS, page 1-2. IEEE, (2015)Time-multiplexed test access architecture for stacked integrated circuits., , , and . IEICE Electron. Express, 13 (14): 20160314 (2016)Erratum to "Time-Multiplexed-Network for Test Cost Reduction"., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (9): 1912 (2018)Scan-Puf: Puf Elements Selection Methods for Viable IC Identification., , , and . ATS, page 121-126. IEEE Computer Society, (2015)Test Architecture for Systolic Array of Edge-Based AI Accelerator., , , , and . IEEE Access, (2021)SONAR Based Obstacle Detection and Avoidance Algorithm., and . ICSAP, page 98-102. IEEE Computer Society, (2009)Time-Multiplexed 1687-Network for Test Cost Reduction., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1681-1691 (2018)On Diagnosing the Aging Level of Automotive Semiconductor Devices., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (7): 822-826 (2017)Reliable Test Architecture With Test Cost Reduction for Systolic-Based DNN Accelerators., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1537-1541 (2022)Highly Efficient Test Architecture for Low-Power AI Accelerators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (8): 2728-2738 (2022)