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Efficient diagnosis technique for aging defects on automotive semiconductor chips.

, , , , and . ETS, page 1-2. IEEE, (2015)

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The educational use of home robots for children., , , and . RO-MAN, page 378-383. IEEE, (2005)Efficient Interconnect Test Patterns for Crosstalk and Static Faults., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (11): 2605-2608 (2006)On Diagnosing the Aging Level of Automotive Semiconductor Devices., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (7): 822-826 (2017)An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (3): 554-565 (2009)Reliable Test Architecture With Test Cost Reduction for Systolic-Based DNN Accelerators., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1537-1541 (2022)Highly Efficient Test Architecture for Low-Power AI Accelerators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (8): 2728-2738 (2022)Design of Test Access Mechanism for AMBA-Based System-on-a-Chip., , , and . VTS, page 375-380. IEEE Computer Society, (2007)Why is less information from logic simulation more useful in fault simulation?, , , and . ITC, page 786-800. IEEE Computer Society, (1990)Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains., , and . ITC, page 1-7. IEEE Computer Society, (2006)An Efficient Secure Scan Design for an SoC Embedding AES Core., , , , , and . ITC, page 1. IEEE Computer Society, (2008)