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A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding., , , and . IEICE Trans. Electron., 100-C (6): 643-654 (2017)Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm., , , , and . IEICE Trans. Electron., 95-C (8): 1415-1426 (2012)Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (4): 1089-1093 (2020)Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (4): 346-350 (2016)A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications., , , , , and . IEEE J. Solid State Circuits, 43 (2): 321-329 (2008)A multi-core mapping implementation of 3780-point FFT., , , , and . ISOCC, page 289-292. IEEE, (2012)ManiDec: Manifold Constrained Low-Rank and Sparse Decomposition., , , , , , and . IEEE Access, (2019)A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1423-1434 (2020)Quarter LCU based integer motion estimation algorithm for HEVC., , , and . ICIP, page 2018-2021. IEEE, (2016)An efficient multi-rate LDPC-CC decoder with layered decoding algorithm., , , and . ICC, page 5548-5552. IEEE, (2013)