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Benchmarking Physical Performance of Neural Inference Circuits., and . CoRR, (2019)Principles and trends in quantum nano-electronics and nano-magnetics for beyond-CMOS computing., and . ESSDERC, page 1-5. IEEE, (2017)Static and Clocked Spintronic Circuit Design and Simulation With Performance Analysis Relative to CMOS., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (2): 393-406 (2014)Gaussian Random Number Generator with Reconfigurable Mean and Variance using Stochastic Magnetic Tunnel Junctions., , , and . CoRR, (2021)Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls., , , , and . CoRR, (2016)A Coupled CMOS Oscillator Array for 8ns and 55pJ Inference in Convolutional Neural Networks., , , , , and . CoRR, (2019)Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking, and . eprint arXiv:cond-mat.mes-hall/1302.0244, (February 2013)Modeling and Design of Spintronic Integrated Circuits., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (12): 2801-2814 (2012)Modeling of Nanoscale Devices., , and . Proc. IEEE, 96 (9): 1511-1550 (2008)Material Targets for Scaling All Spin Logic, , and . CoRR, (2012)