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Known-good-die test methods for large, thin, high-power digital devices.

D. Armstrong, and G. Maier. ITC, page 1-6. IEEE, (2016)

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Alexander Gary

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Max Gary

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Known-good-die test methods for large, thin, high-power digital devices.D. Armstrong, and G. Maier. ITC, page 1-6. IEEE, (2016)ITC 2003 Roundtable: Design for Manufacturability.R. Aitken, S. Eichenberger, G. Maier, S. Kundu, and H. Walker. IEEE Des. Test Comput., 21 (2): 144-156 (2004)Modulation of CNS pain circuitry by intravenous and sublingual doses of buprenorphine.J. Upadhyay, J. Anderson, R. Baumgartner, A. Coimbra, A. Schwarz, G. Pendse, D. Wallin, L. Nutile, J. Bishop, E. George and 9 other author(s). NeuroImage, 59 (4): 3762-3773 (2012)Electronic Process Limited Yield.G. Maier, and S. Smith. ISQED, page 467-474. IEEE Computer Society, (2000)Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias.T. Kirihata, J. Golz, M. Wordeman, P. Batra, G. Maier, N. Robson, T. Graves-abe, D. Berger, and S. Iyer. IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A shorted global clock design for multi-GHz 3D stacked chips.L. Pang, P. Restle, M. Wordeman, J. Silberman, R. Franch, and G. Maier. VLSIC, page 170-171. IEEE, (2012)Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias.M. Wordeman, J. Silberman, G. Maier, and M. Scheuermann. ISSCC, page 186-187. IEEE, (2012)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)

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Disambiguation of "Maier, Gary"

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Known-good-die test methods for large, thin, high-power digital devices.

Please choose a person to relate this publication to

Alexander Gary

Klaus Gary

Regina Gary

Bente Gary

Max Gary

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Maier, Gary"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Known-good-die test methods for large, thin, high-power digital devices.

Please choose a person to relate this publication to

Alexander Gary

Klaus Gary

Regina Gary

Bente Gary

Max Gary

Other publications of authors with the same name

Disambiguation

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DOI
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Chicago
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Known-good-die test methods for large, thin, high-power digital devices.