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A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application.

P. Dong, Z. Chen, Z. Li, Y. Fu, L. Chen, and F. An. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (1): 334-346 (2022)

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Fengwei Wang

Fengwei Guo

Fengwei Li

An You

An Mengi

Other publications of authors with the same name

k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching.F. An, L. Chen, T. Akazawa, S. Yamazaki, and H. Mattausch. IEICE Trans. Electron., 99-C (3): 397-403 (2016)A Reconfigurable Coprocessor for Simultaneous Localization and Mapping Algorithms in FPGA.Y. Tan, H. Deng, M. Sun, M. Zhou, Y. Chen, L. Chen, C. Wang, and F. An. IEEE Trans. Circuits Syst. II Express Briefs, 70 (1): 286-290 (2023)Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction.Y. Fujita, F. An, A. Luo, X. Zhang, L. Chen, and H. Mattausch. APCCAS, page 611-612. IEEE, (2016)A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices.P. Xu, Z. Xiao, X. Wang, L. Chen, C. Wang, and F. An. Sensors, 20 (21): 6239 (2020)BESA: Pruning Large Language Models with Blockwise Parameter-Efficient Sparsity Allocation.P. Xu, W. Shao, M. Chen, S. Tang, K. Zhang, P. Gao, F. An, Y. Qiao, and P. Luo. CoRR, (2024)A Dynamic Codec with Adaptive Quantization for Convolution Neural Network.Y. Ouyang, X. Wang, G. Shi, L. Chen, and F. An. ASICON, page 1-4. IEEE, (2023)A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching.P. Dong, Z. Li, Z. Chen, R. Yao, H. Deng, W. Zhang, Y. Zhang, L. Chen, C. Wang, and F. An. A-SSCC, page 1-3. IEEE, (2021)A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots.J. Wang, Y. Zhan, Z. Wang, Z. Peng, J. Xu, B. Liu, G. Yu, F. An, C. Wang, and X. Zou. A-SSCC, page 1-3. IEEE, (2021)Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA.Y. Ma, X. Fang, P. Dong, X. Guan, K. Li, L. Chen, and F. An. SOCC, page 1-5. IEEE, (2022)A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier.A. Luo, F. An, X. Zhang, and H. Mattausch. IEEE Access, (2019)

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Disambiguation of "An, Fengwei"

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A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application.

Please choose a person to relate this publication to

Fengwei Wang

Fengwei Guo

Fengwei Li

An You

An Mengi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "An, Fengwei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application.

Please choose a person to relate this publication to

Fengwei Wang

Fengwei Guo

Fengwei Li

An You

An Mengi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application.