Author of the publication

Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (5): 893-905 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Adversarially Robust Learning via Entropic Regularization., , , and . CoRR, (2020)On Evaluating Neural Network Backdoor Defenses., and . CoRR, (2020)BandiTS: Dynamic timing speculation using multi-armed bandit based optimization., and . DATE, page 922-925. IEEE, (2017)Low cost permanent fault detection using ultra-reduced instruction set co-processors., , and . DATE, page 933-938. EDA Consortium San Jose, CA, USA / ACM DL, (2013)EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip., , , and . FPL, page 41-48. IEEE, (2012)Fragility of the Commons under Prospect-Theoretic Risk Attitudes., , and . CoRR, (2014)Exploiting Process Variability in Voltage/Frequency Control., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (8): 1392-1404 (2012)Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements., , and . ISQED, page 96-103. IEEE, (2013)A Feature-Based On-Line Detector to Remove Adversarial-Backdoors by Iterative Demarcation., , , , and . IEEE Access, (2022)Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (8): 2580-2590 (2023)