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A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.

C. Huang, C. Liu, C. Wang, Y. Chen, S. Datta, and V. Narayanan. ASP-DAC, page 118-123. IEEE, (2015)

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Yao Wang

Wang Yao

Chun Wang

Other publications of authors with the same name

Low-Latency Service Chaining With Predefined NSH-Based Multipath Across Multiple Datacenters.Y. Wang, R. Hwang, and Y. Lin. IEEE Trans. Netw. Serv. Manag., 19 (4): 4721-4733 (December 2022)LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach.X. Yang, P. Chen, H. Chiang, C. Lin, Y. Chen, and C. Wang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (1): 29-34 (2022)IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement.T. Wang, Y. Chang, C. Chen, Y. Lee, C. Lin, Y. Chen, and C. Wang. ISQED, page 173-178. IEEE, (2020)Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.Y. Li, C. Huang, C. Wu, Y. Chen, C. Wang, S. Datta, and V. Narayanan. IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1477-1489 (2017)Error Injection & Correction: An efficient formal logic restructuring algorithm.C. Huang, D. Lee, C. Lin, and C. Wang. ISOCC, page 188-191. IEEE, (2012)High level equivalence symmetric input identification.M. Su, and C. Wang. ASP-DAC, page 249-253. IEEE, (2006)On reconfigurable single-electron transistor arrays synthesis using reordering techniques.C. Chiang, L. Tang, C. Wang, C. Huang, Y. Chen, S. Datta, and V. Narayanan. DATE, page 1807-1812. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Efficient synthesis of approximate threshold logic circuits with an error rate guarantee.Y. Lai, C. Lin, C. Wu, Y. Chen, and C. Wang. DATE, page 773-778. IEEE, (2018)A register-transfer level testability analyzer.Y. Chen, C. Wang, C. Huang, and H. Lin. SoCC, page 219-224. IEEE, (2011)A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli.H. Liu, Y. Li, Y. Chen, and C. Wang. ASP-DAC, page 696-701. ACM, (2023)

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Disambiguation of "Wang, Chun-Yao"

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A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.

Please choose a person to relate this publication to

Yao Wang

Wang Yao

Chun Wang

Chun Wang

Chun Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Chun-Yao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.

Please choose a person to relate this publication to

Yao Wang

Wang Yao

Chun Wang

Chun Wang

Chun Wang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
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A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.