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Disambiguation of "Oklobdzija, Vojin G."

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Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs.

, and . IEEE Symposium on Computer Arithmetic, page 280. IEEE Computer Society, (2003)

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Vojin ivojnovi

Krunoslav Vojinovi

Vojin Smodlaka

Vojin Drenovac

Giuseppe G G Manzardo

 

Other publications of authors with the same name

Partitioned Branch Condition Resolution Logic., , and . SBCCI, page 35-40. IEEE Computer Society, (2000)Some optimal schemes for ALU implementation in VLSI technology., and . IEEE Symposium on Computer Arithmetic, page 2-8. IEEE, (1985)Issues in CPU-coprocessor communication and synchronization.. Microprocess. Microprogramming, 24 (1-5): 695-700 (1988)Low-Power Soft Error Hardened Latch., and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 256-265. Springer, (2009)Future directions in clocking multi-ghz systems., and . ISLPED, page 219. ACM, (2002)Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation., , and . ISLPED, page 56-59. ACM, (2001)Conditional pre-charge techniques for power-efficient dual-edge clocking., , and . ISLPED, page 56-59. ACM, (2002)A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 724-732. Springer, (2005)An integrated multiplier for complex numbers., , and . VLSI Signal Processing, 7 (3): 213-222 (1994)Timing Characterization of Dual-edge Triggered Flip-flops., , and . ICCD, page 538-541. IEEE Computer Society, (2001)