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Conditional pre-charge techniques for power-efficient dual-edge clocking.

, , and . ISLPED, page 56-59. ACM, (2002)

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Comparative analysis of double-edge versus single-edge triggered clocked storage elements., , and . ISCAS (5), page 105-108. IEEE, (2002)A new CFA interpolation framework., , , and . Signal Process., 86 (7): 1559-1579 (2006)Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (10): 3038-3049 (2008)Coding for the blackwell channel: a survey propagation approach., and . ISIT, page 1583-1587. IEEE, (2005)Conditional techniques for low power consumption flip-flops., , and . ICECS, page 803-806. IEEE, (2001)A novel cost effective demosaicing approach., , , and . IEEE Trans. Consumer Electronics, 50 (1): 256-261 (2004)Conditional pre-charge techniques for power-efficient dual-edge clocking., , and . ISLPED, page 56-59. ACM, (2002)A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 724-732. Springer, (2005)Timing Characterization of Dual-edge Triggered Flip-flops., , and . ICCD, page 538-541. IEEE Computer Society, (2001)Capacity of a Class of Modulo-Sum Relay Channels., , and . IEEE Trans. Inf. Theory, 55 (3): 921-930 (2009)