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Integrated Placement for Mixed Macro Cell and Standard Cell Designs., , and . DAC, page 32-35. IEEE Computer Society Press, (1990)Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance., , , , and . IEEE Micro, 24 (6): 62-73 (2004)A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 36 (11): 1617-1627 (2001)The gem5 Simulator: Version 20.0+., , , , , , , , , and 63 other author(s). CoRR, (2020)Architectural trade-offs in a latency-tolerant gallium arsenide microprocessor.. University of Michigan, USA, (1997)The Impact of Performance Asymmetry in Emerging Multicore Architectures., , , and . ISCA, page 506-517. IEEE Computer Society, (2005)Resource Allocation in a High Clock Rate Microprocessor., , , and . ASPLOS, page 98-109. ACM Press, (1994)Continual flow pipelines., , , , and . ASPLOS, page 107-119. ACM, (2004)A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus., , , , and . MICRO, page 31-40. ACM / IEEE Computer Society, (1993)