Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications., , , , , , , , , and 2 other author(s). IRPS, page 2-1. IEEE, (2018)Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (5): 748-752 (2019)High speed and high-area efficiency non-volatile look-up table design based on magnetic tunnel junction., , , and . NVMTS, page 1-4. IEEE, (2017)Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse., , , , , , , , and . AICAS, page 136-140. IEEE, (2020)OTS selector devices: Material engineering for switching performance., , , , , , , , and . ICICDT, page 113-116. IEEE, (2018)Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations., , , , , , , , , and . IEEE Access, (2020)Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization., , , , , , , , , and 4 other author(s). IRPS, page 1-6. IEEE, (2021)Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays., , , , , , , and . CoRR, (2019)High density SOT-MRAM memory array based on a single transistor., , , and . NVMTS, page 1-3. IEEE, (2018)In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications., , , , , , , and . DATE, page 690-695. IEEE, (2020)