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Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. ITC, page 488-493. IEEE Computer Society, (2003)

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Marc Bonhomme

Stéphane Bonhomme

Oriane Bonhomme

Yannick Zakowski

Yannick Carlinet

Other publications of authors with the same name

Programmable extended SEC-DED codes for memory errors.V. Gherman, S. Evain, F. Auzanneau, and Y. Bonhomme. VTS, page 140-145. IEEE Computer Society, (2011)Memory reliability improvements based on maximized error-correcting codes.V. Gherman, S. Evain, and Y. Bonhomme. European Test Symposium, page 1-6. IEEE Computer Society, (2012)Memory Reliability Improvement Based on Maximized Error-Correcting Codes.V. Gherman, S. Evain, and Y. Bonhomme. J. Electron. Test., 29 (4): 601-608 (2013)Power-Driven Routing-Constrained Scan Chain Design.Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. J. Electron. Test., 20 (6): 647-660 (2004)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.S. Sarrazin, S. Evain, L. de Barros Naviner, Y. Bonhomme, and V. Gherman. DATE, page 1077-1082. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Programmable restricted SEC codes to mask permanent faults in semiconductor memories.S. Evain, Y. Bonhomme, and V. Gherman. IOLTS, page 147-153. IEEE Computer Society, (2010)An efficient scan tree design for test time reduction.Y. Bonhomme, T. Yoneda, H. Fujiwara, and P. Girard. ETS, page 174-179. IEEE Computer Society, (2004)Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. ITC, page 488-493. IEEE Computer Society, (2003)Power Driven Chaining of Flip-Flops in Scan Architectures.Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch. ITC, page 796-803. IEEE Computer Society, (2002)Generalized parity-check matrices for SEC-DED codes with fixed parity.V. Gherman, S. Evain, N. Seymour, and Y. Bonhomme. IOLTS, page 198-201. IEEE Computer Society, (2011)

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Disambiguation of "Bonhomme, Yannick"

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URL
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Chicago
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Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Please choose a person to relate this publication to

Marc Bonhomme

Stéphane Bonhomme

Oriane Bonhomme

Yannick Zakowski

Yannick Carlinet

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bonhomme, Yannick"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Please choose a person to relate this publication to

Marc Bonhomme

Stéphane Bonhomme

Oriane Bonhomme

Yannick Zakowski

Yannick Carlinet

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.