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Disambiguation of "Landrault, Christian"

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Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

, , , , and . ITC, page 488-493. IEEE Computer Society, (2003)

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Christian Christian

Christian Winter

Gold-katalysierte Cycloisomerisierung funktionalisierter Allene und Anwendung in der Naturstoffsynthese. TU Dortmund, (2009)

Christian Helbig

Synthese und Charakterisierung von metallorganischen Bronzen. Uni Augsburg, (2009)

Christian Schüller

Automatisierte Feedbackgenerierung in der benutzerzentrierten Softwareentwicklung am Beispiel mobiler Anwendungen. TU München, (2009)

Christian Haase

Diabetes mellitus Typ1 und Schwangerschaft: Entwicklung von Morbiditäts- und Mortalitätskriterien 1990 - 2004 ; eine Datenanalyse der Hessischen Perinatalerhebung (HEPE). Uni Marburg, (2009)
 

Other publications of authors with the same name

High Defect Coverage with Low-Power Test Sequences in a BIST Environment., , , , and . IEEE Des. Test Comput., 19 (5): 44-52 (2002)Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis., , , and . EDAC-ETC-EUROASIC, page 518-523. IEEE Computer Society, (1994)Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences., , , , and . J. Electron. Test., 17 (3-4): 233-241 (2001)A Gated Clock Scheme for Low Power Testing of Logic Cores., , , , , and . J. Electron. Test., 22 (1): 89-99 (2006)Low power BIST design by hypergraph partitioning: methodology and architectures., , , and . ITC, page 652-661. IEEE Computer Society, (2000)An adjacency-based test pattern generator for low power BIST design., , , and . Asian Test Symposium, page 459-464. IEEE Computer Society, (2000)Generalized Distributed Comparison-Based System-Level Diagnosis., , , , , and . LATW, page 285-290. IEEE, (2001)A Gated Clock Scheme for Low Power Scan-Based BIST., , , , and . IOLTW, page 87-89. IEEE Computer Society, (2001)An optimized BIST test pattern generator for delay testing., , , and . VTS, page 94-100. IEEE Computer Society, (1997)A Test Vector Inhibiting Technique for Low Energy BIST Design., , , and . VTS, page 407-412. IEEE Computer Society, (1999)