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Analytical performance comparison of 2D Mesh, WK-recursive, and Spidergon NoCs., , , and . IPDPS Workshops, page 1-6. IEEE, (2010)Performance Analysis Techniques in SOC Design., , and . ESA/VLSI, page 249-255. CSREA Press, (2004)Analytical modeling and evaluation of network-on-chip architectures., , , and . HPCS, page 615-622. IEEE, (2010)Performance evaluation and design tradeoffs of on-chip interconnect architectures., , , , and . Simul. Model. Pract. Theory, 19 (6): 1496-1505 (2011)Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus., , , and . NOCS, page 74-79. IEEE Computer Society, (2009)Methodology for adapting on-chip interconnect architectures., , , , and . IET Comput. Digit. Tech., 8 (3): 109-117 (2014)Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network., , and . NOCS, page 205-206. IEEE Computer Society, (2008)A Computational Intellegence Approach for Parametrized SoC Optimization., and . ESA/VLSI, page 596-600. CSREA Press, (2004)An interconnection architecture for network-on-chip systems., , , and . Telecommun. Syst., 37 (1-3): 137-144 (2008)A scalability study of interconnect architectures for System-on-Chip., , , and . HPCS, page 300-306. IEEE, (2012)