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RRAM Reliability/Performance Characterization through Array Architectures Investigations.

, , , , and . ISVLSI, page 327-332. IEEE Computer Society, (2015)

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A novel critical path heuristic for fast fault grading., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (4): 544-548 (1991)Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers., , , , , , and . ACM Trans. Embed. Comput. Syst., 14 (1): 7:1-7:24 (2015)Design space exploration of latency and bandwidth in RRAM-based solid state drives., , , , and . NVMTS, page 1-4. IEEE, (2015)RRAM Reliability/Performance Characterization through Array Architectures Investigations., , , , and . ISVLSI, page 327-332. IEEE Computer Society, (2015)On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing., , and . ITC, page 936. IEEE Computer Society, (1989)Reliability and cell-to-cell variability of TAS-MRAM arrays under cycling conditions., , , , and . NVMTS, page 1-4. IEEE, (2015)Detection of PLA multiple crosspoint faults., , , and . EURO-DAC, page 80-84. EEE Computer Society, (1991)Automated characterization of TAS-MRAM test arrays., , , , , , and . DTIS, page 1-2. IEEE, (2015)System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems., , , , and . ISSoC, page 1-6. IEEE, (2013)Reliability evaluation of combinational logic circuits by symbolic simulation., , , and . VTS, page 235-243. IEEE Computer Society, (1995)