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A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction., , , , , , and . J. Electron. Test., 24 (4): 353-364 (2008)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)Parity prediction synthesis for nano-electronic gate designs., , , , , , and . ITC, page 820. IEEE Computer Society, (2010)Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption., , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)A new test pattern generation method for delay fault testing., , , , and . VTS, page 296-301. IEEE Computer Society, (1996)Failure Analysis and Test Solutions for Low-Power SRAMs., , , , , , , and . Asian Test Symposium, page 459-460. IEEE Computer Society, (2011)Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies., , , , and . DAC, page 857-862. ACM, (2005)Comprehensive bridging fault diagnosis based on the SLAT paradigm., , , , , , , and . DDECS, page 264-269. IEEE Computer Society, (2009)Defect Analysis for Delay-Fault BIST in FPGAs., , , and . IOLTS, page 124-128. IEEE Computer Society, (2003)On Using Efficient Test Sequences for BIST., , , , and . VTS, page 145-152. IEEE Computer Society, (2002)