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A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1942-1955 (2019)Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects., , and . J. Electron. Test., 28 (1): 39-51 (2012)Physics-Based Low-Cost Test Technique for High Voltage LDMOS., , , , , , , and . J. Electron. Test., 29 (6): 745-762 (2013)Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper)., , and . ICCAD, page 55. ACM, (2016)Automatic diagnostic tool for Analog-Mixed Signal and RF load boards., and . ITC, page 1. IEEE Computer Society, (2009)Modeling and characterization of CNT-based TSV for high frequency applications., , , , , and . ISCAS, page 1584-1589. IEEE, (2012)Impact of TSV integration on 14nm FinFET device performance., , , and . 3DIC, page 1-5. IEEE, (2016)Compact Scalable Dynamic TSV IR Drop Compensation for Power Delivery in 3D Packages., , , and . MWSCAS, page 1179-1182. IEEE, (2019)Accelerating Artificial Intelligence with Silicon Photonics., , , , , , , , , and 11 other author(s). OFC, page 1-4. IEEE, (2020)Physics Based Fault Models for Testing High-Voltage LDMOS., , , , , and . VLSI Design, page 285-290. IEEE Computer Society, (2013)