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Disambiguation of "Schaal, Marcel"

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IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory.

, , , , , , , and . IBM J. Res. Dev., 57 (1/2): 7 (2013)

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Janina Schaal

Heiner Schaal

Gerhard Schaal

Walter Schaal

Dietmar Schaal

 

Other publications of authors with the same name

Efficient AI System Design With Cross-Layer Approximate Computing., , , , , , , , , and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator., , , , , , , , , and 3 other author(s). IEEE Micro, 39 (5): 102-111 (2019)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference., , , , , , , , , and 44 other author(s). ISCA, page 153-166. IEEE, (2021)14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC., , , , , , , , , and 36 other author(s). ISSCC, page 254-256. IEEE, (2024)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Efficient fault simulation on many-core processors., , , and . DAC, page 380-385. ACM, (2010)