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Disambiguation of "Ostúa, Enrique"

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Long-term on-chip verification of systems with logical events scattered in time.

, , , , , and . Microprocess. Microsystems, 36 (5): 402-408 (2012)

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Enrique Casanovas

Enrique Lozano

Enrique Gaviola

Enrique Barros

Enrique Knorr

 

Other publications of authors with the same name

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , and . IES, page 1-7. IEEE, (2006)Improving the Performance of Static CMOS Gates by Using Independent Bodies., , , , , , and . J. Low Power Electron., 3 (1): 70-77 (2007)Accurate Logic-Level Current Estimation for Digital CMOS Circuits., , , , , , and . J. Low Power Electron., 2 (1): 87-94 (2006)Minimalistic SDHC-SPI hardware reader module for boot loader applications., , , , , and . Microelectron. J., (2017)Static Power Consumption in CMOS Gates Using Independent Bodies., , , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)Signal Sampling Based Transition Modeling for Digital Gates Characterization., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 829-837. Springer, (2004)Long-term on-chip verification of systems with logical events scattered in time., , , , , and . Microprocess. Microsystems, 36 (5): 402-408 (2012)Design and implementation of a suitable core for on-chip long-term verification., , , , , and . SIES, page 234-237. IEEE, (2010)Using the complement of the cosine to compute trigonometric functions., , , , , , and . EURASIP J. Adv. Signal Process., 2020 (1): 1-21 (2020)Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells., , , , , , and . J. Low Power Electron., 7 (3): 444-452 (2011)