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X-clock routing based on pattern matching., , , , и . SoCC, стр. 357-360. IEEE, (2008)Coupling aware RLC-based clock routings for crosstalk minimization., , , , и . ISCAS, IEEE, (2006)Antenna Violation Avoidance/Fixing for X-clock routing., , , и . ISQED, стр. 508-514. IEEE, (2010)An H-V Tile-Expansion Router., , и . J. Inf. Sci. Eng., 6 (3): 173-189 (1990)Using Stack Reconstruction on RTL Orthogonal Scan Chain Design., , , , и . J. Inf. Sci. Eng., 22 (6): 1585-1599 (2006)Generalized terminal connectivity problem for multilayer layout scheme., , и . Comput. Aided Des., 22 (7): 423-433 (1990)Performance driven bus buffer insertion., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (4): 429-437 (1996)NEWS: a net-even-wiring system for the routing on a multilayer PGA package., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (2): 182-189 (1998)An H-V alternating router., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (8): 976-991 (1992)A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters., , и . Journal of Circuits, Systems, and Computers, 18 (5): 933-945 (2009)