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Disambiguation of "Deng, Marina"

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InP DHBT test structure optimization towards 110 GHz characterization.

, , , , , , , and . ESSDERC, page 320-323. IEEE, (2022)

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Zhiguo Deng

Petra Deng

Yiming Deng

Mario Deng

Ming Deng

 

Other publications of authors with the same name

InP DHBT Analytical Modeling: Toward THz Transistors., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4102-4111 (November 2023)Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors., , , , , , , , , and 2 other author(s). VLSI-SoC, page 1-2. IEEE, (2022)3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model., , , , , , , , , and 1 other author(s). VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 301-321. Springer, (2020)2D RF Electronics: from devices to circuits - challenges and applications., , , , , , , , and . DRC, page 1-2. IEEE, (2018)0.4-μm InP/InGaAs DHBT with a 380-GHz $f_T$, > 600-GHz $f_\max$ and BVCE0 > 4.5 V., , , , , , , and . BCICTS, page 1-4. IEEE, (2021)SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design., , , , , , , , , and 3 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 3045-3052 (September 2023)3D logic cells design and results based on Vertical NWFET technology including tied compact model., , , , , , , , , and . CoRR, (2020)InP DHBT test structure optimization towards 110 GHz characterization., , , , , , , and . ESSDERC, page 320-323. IEEE, (2022)Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design., , , , , , , , , and . ESSDERC, page 57-60. IEEE, (2023)Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance., , , , , , , , , and 1 other author(s). BCICTS, page 1-7. IEEE, (2021)