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Disambiguation of "Shin, Jinuk Luke"

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The Next Generation 64b SPARC Core in a T4 SoC Processor.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 48 (1): 82-90 (2013)

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Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen Konzil. Uni München, (2009)

Friedmar Lüke

Hermann Lüke

Werner Luke

 

Other publications of authors with the same name

AI SoC Design Challenges in the Foundation Model Era., , , , , , , , , and 9 other author(s). CICC, page 1-8. IEEE, (2023)Session 4 overview: Processors: High-performance digital subcommittee., and . ISSCC, page 68-69. IEEE, (2015)Bandwidth and power management of glueless 8-socket SPARC T5 system., , , and . ISSCC, page 58-59. IEEE, (2013)Design and implementation of an embedded 512-KB level-2 cache subsystem., , , and . IEEE J. Solid State Circuits, 40 (9): 1815-1820 (2005)The UltraSPARC T1 Processor: CMT Reliability., , and . CICC, page 555-562. IEEE, (2006)A Power-Efficient High-Throughput 32-Thread SPARC Processor., , , , , , , and . ISSCC, page 295-304. IEEE, (2006)A dual-core 64b ultraSPARC microprocessor for dense server applications., , , , and . DAC, page 673-677. ACM, (2004)A 40nm 16-core 128-thread CMT SPARC SoC processor., , , , , , , , , and 3 other author(s). ISSCC, page 98-99. IEEE, (2010)Session 3 overview: Processors: High performance digital subcommittee., and . ISSCC, page 54-55. IEEE, (2012)SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0., , and . ISSCC, page 350-352. IEEE, (2022)