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Software-directed power-aware interconnection networks.

, , and . ACM Trans. Archit. Code Optim., 4 (1): 5 (2007)

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Designing High-Performance, Power-Efficient NoCs With Embedded Silicon-in-Silica Nanophotonics., , , and . NOCS, page 30:1-30:2. ACM, (2015)Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks., and . IEEE Trans. Parallel Distributed Syst., 18 (3): 393-408 (2007)An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets., , , , , and . CoRR, (2019)Intelligent NOC Hotspot Prediction., , and . ISVLSI (Selected papers), volume 105 of Lecture Notes in Electrical Engineering, page 3-16. Springer, (2010)Intelligent On/Off Link Management for On-chip Networks., , and . ISVLSI, page 343-344. IEEE Computer Society, (2011)Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability., , , and . ISVLSI, page 21-26. IEEE Computer Society, (2012)Intelligent On/Off Dynamic Link Management for On-Chip Networks., , and . J. Electr. Comput. Eng., (2012)Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths., , and . IET Comput. Digit. Tech., (2013)Toward Fault-Tolerant Deadlock-Free Routing in HyperSurface-Embedded Controller Networks., , , , and . IEEE Netw. Lett., 2 (3): 140-144 (2020)Interposer-Based Root of Trust., , , , , and . CoRR, (2021)