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Disambiguation of "Zou, Qiaosha"

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Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.

, , , , , and . DAC, page 173:1-173:6. ACM, (2016)

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Yang Zou

Peiguo Zou

Zhurong Zou

Yang Zou

Lijie Zou

 

Other publications of authors with the same name

AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 2994-3006 (September 2023)Compact models and model standard for 2.5D and 3D integration., and . SLIP, page 7:1-7:7. IEEE Computer Society, (2014)Overview of 3-D Architecture Design Opportunities and Techniques., , and . IEEE Des. Test, 34 (4): 60-68 (2017)Thermomechanical Stress-Aware Management for 3-D IC Designs., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (9): 2678-2682 (2017)3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs., , , and . DATE, page 1185-1190. IEEE, (2012)System-level design space exploration for three-dimensional (3D) SoCs., , , and . CODES+ISSS, page 385-388. ACM, (2011)3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code., , , and . ASP-DAC, page 762-767. IEEE, (2014)SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos., , , , , , and . IEEE Trans. Hum. Mach. Syst., 52 (1): 110-122 (2022)A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 10 (3): 283-294 (2020)TSV power supply array electromigration lifetime analysis in 3D ICS., , , and . ACM Great Lakes Symposium on VLSI, page 239-240. ACM, (2014)