From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning., , , и . ISVLSI, стр. 392-397. IEEE Computer Society, (2015)Mesh-of-Tree Based Scalable Network-on-Chip Architecture., , , и . ICIIS, стр. 1-6. IEEE, (2008)Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (8): 2249-2262 (августа 2024)Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization., , , и . VDAT, том 382 из Communications in Computer and Information Science, стр. 74-82. Springer, (2013)A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic., , , , , и . ARTCom, стр. 414-418. IEEE Computer Society, (2009)A spare router based reliable Network-on-Chip design., , и . ISCAS, стр. 1957-1960. IEEE, (2014)A Novel Technique to Reduce both Leakage and Peak Power during Scan Testing., , и . ICIIS, стр. 1-6. IEEE, (2008)Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip., , и . VLSI-SoC, стр. 1-6. IEEE, (2014)Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs., , , и . ISVLSI, стр. 529-534. IEEE Computer Society, (2016)Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip., , и . ISVLSI, стр. 583-586. IEEE Computer Society, (2016)