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Disambiguation of "Viraraghavan, Janakiraman"

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A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.

, , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)

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Umamaheswari Janakiraman

Narayanan Janakiraman

 

Other publications of authors with the same name

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter., and . ISCAS, page 1-5. IEEE, (2021)Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (7): 1056-1069 (2010)A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)Statistical compact model extraction for skew-normal distributions., and . IET Circuits Devices Syst., 14 (5): 576-585 (2020)Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks., , and . J. Low Power Electron., 4 (3): 301-319 (2008)Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study., and . ISCAS, page 1-5. IEEE, (2020)Statistical Compact Model Extraction: A Neural Network Approach., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1920-1924 (2012)Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection., and . IEEE Trans. Educ., 66 (1): 83-93 (February 2023)80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 53 (3): 949-960 (2018)Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations., , , , and . VLSI Design, page 685-691. IEEE Computer Society, (2008)