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Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip., , , , , , , , and . ARITH, page 37-44. IEEE, (2018)Hardware Implementation of an OPC UA Server for Industrial Field Devices., , , , , , , , , and 6 other author(s). CoRR, (2021)Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 10 other author(s). ISCAS, page 1. IEEE, (2017)A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI., , , , , , , , , and 3 other author(s). IEEE Trans. Biomed. Circuits Syst., 16 (1): 94-107 (2022)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)True random number generation from bang-bang ADPLL jitter., , , and . NORCAS, page 1-5. IEEE, (2016)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). CoRR, (2019)A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI., , , , , , , and . AICAS, page 1-5. IEEE, (2023)The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing., , , , , , , , , and 8 other author(s). CoRR, (2021)