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Disambiguation of "Yoshimura, Masayoshi"

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A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT.

, , , and . DFT, page 1-6. IEEE, (2020)

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Tateo Yoshimura

Tadasuke Yoshimura

 

Other publications of authors with the same name

Controller augmentation and test point insertion at RTL for concurrent operational unit testing., , , and . IOLTS, page 17-20. IEEE, (2017)A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns., , , and . IOLTS, page 228-231. IEEE, (2018)A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method., , , , and . IOLTS, page 1-4. IEEE, (2020)A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively., , , , , and . DFT, page 1-6. IEEE, (2019)A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths., , , and . IOLTS, page 293-298. IEEE, (2019)An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing., , , and . DFT, page 1-6. IEEE, (2023)Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure., , , , , , , , and . IOLTS, page 151-156. IEEE Computer Society, (2011)Collaborative optimization for product design and manufacturing.. CAD, page 1-16. GI German Informatics Society, (2002)A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification., , , , , , and . IOLTS, page 43-46. IEEE, (2018)Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times., , and . ASP-DAC, page 485-491. ACM, (2001)